Design And Reuse SoC News Alert

December 21, 2004

Michael,
Welcome to issue of December 21, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: eASIC, Corp.

NRE-free Structured ASIC

ASIC-like unit-cost, power and performance

FPGA-like ease of design (SRAM-LUT)

Flexible exchange between logic and distributed memory

No minimum volume required

Turnaround: < 2 weeks

Built-in clock tree, BIST, scan chain and power distribution

Easy post-fabrication debug - LUT reload

Variety of configurable I/Os

Embedded 8051 microcontroller

DES and 3DES cipher capable of 1+ Gbps performance from Elliptic Semiconductor

MMC 4.0 Card Controller Compliance Suite from Arasan Chip Systems

PDKChek, Independent die-level monitor Semiconductor IP from Ridgetop Group

AXI Monitor & AXI Interconnect from Synopsys

Dual Mode 5 Channel Junction Temperature Measurement System from ChipIdea Microelectronics

Bridging a gap with peripherals

Mixed-level modeling allows IC virtual prototypes

SoC package design takes 'bottom-up' tack

SiPs offer alternative to SoCs for comms

Multicore designs might force Intel off its bus; Integrated memory controllers may loom large in future designs

The CTO interview: with Ivo Bolsens of Xilinx

Dialogue with Sir Robin Saxby

IP/SOC PRODUCTS

SafeNet Releases Expanded Line of High Performance SafeXcel IP Security Engines

STMicroelectronics Wins the Race to Deliver First 65-nm CMOS Design Platform

Toshiba and NEC Develop Key Technologies for High-Density MRAM

STRUCTURED ASIC

Structured ASIC: The Next-Generation Design Technology, Frost & Sullivan Says

eASIC Granted 11th Patent for its Configurable Logic Technology

DEALS

LG Electronics Chooses SH-Mobile for Mobile Phone Handsets

Atmel Licenses Industry-Leading Gigabit Ethernet Physical Layer Core From National Semiconductor To Power Its Next-Generation Of High Performance System-on-Chip

Artisan IP Selected by Sandburst for Advanced HIBEAM Chipset; Silicon-Proven IP and Ease of Use Enabled Sandburst's First-Pass Silicon

Saifun Signs Memory Technology Licensing Agreement with Sony

Ubicom Selects Denali's Verification IP Products for Chip Development Efforts

BUSINESS

IRG Research Initiates Coverage of MIPS Technologies with "Buy"

HeJian Technology and Artisan Collaborate to Deliver 0.18-Micron Process IP Solutions

Worldwide Semiconductor Capital Equipment Spending to Decline by 15 Percent in 2005

Flextronics acquires Deccanet

FINANCIAL RESULTS

Silicon Storage Technology (SST) Updates Guidance on Expected Fourth Quarter 2004 Results

EMBEDDED SYSTEMS

Upgrade to Accelerated Technology's Nucleus Point-to-Point Protocol Software Benefits Embedded Networking Developers

Renesas Technology and Discretix Team to Deploy Embedded Security Solutions Using SH-Mobile Processors for 2.5 and 3G Mobile Handsets

GDA Technologies and Ample Communications Announce Ethernet Switching and Routing Reference Platform

FOUNDRIES

Artisan IP Solutions Selected by HHNEC for 0.18-Micron Process

IBM, Samsung, Infineon, Chartered describe 65-nm process

FPGA/CPLD

Avnet Electronics Marketing Announces Immediate Availability Of Xilinx ATCA Design Kit

EDA

Tool vendors dispute report of downturn in ESL

CoWare to Showcase Leading Solutions for Electronic System Level (ESL) Design at VLSI Design 2005 & ICES Conference in Kolkata India, Jan. 3-5, 2005

OTHER

PCI-SIG Announces PCI Express Architecture Performance Extension

ZigBee Alliance Finalizes Specification

ARC International Named Among UK's "Fast 50" Growth Companies in Annual Deloitte Rankings

Virtual Silicon's Mobilize Named as Finalist for DesignCon 2004 Design Vision Award

Mentor Graphics Joins Serial ATA International Organization

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento

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